As to LSIs including System On Chip (SOC) and microcomputers (MC), larger-scale integration, higher functionality and higher-speed operation have been achieved with the rapid progress in semiconductor manufacturing techniques. However, on the other hand, the demands for subtle power management to suppress the increase in leak current on standby and high-speed restore are growing particularly in regard to battery-driven portable devices and something of that sort. Specifically, the operation of an internal circuit of LSI to reduce leak current on standby must include shift to a sleep mode in which supply of a clock to the internal circuit is stopped on standby, and rapid resumption of the clock supply at the time of making the internal circuit resume working in an active mode.
Clock generating circuits based on the frequency of a clock input signal and/or the phase of the pulse edge are roughly classified into the following three circuits.
The first circuit is PLL (Phase Locked Loop). The frequency of an output clock thereof is a multiple of the frequency of an input clock in general. PLL incorporates a phase comparator and a variable-phase circuit. Therefore, in PLL, control is performed so that the phase of a feedback clock resulting from frequency division of an output clock, by which the frequency is made equal to the output clock frequency times the reciprocal of a multiplication number, is essentially made coincident with (or locked to) the phase of an input clock.
The second circuit is DLL (Delay Locked Loop), which delays an input clock thereby produce an output clock. DLL incorporates a phase comparator and a variable delay circuit, by which control is performed so that the phase of an output clock produced by the variable delay circuit is behind by a fixed value with respect to the phase of an input clock essentially.
The third circuit is FLL (Frequency Locked Loop). The frequency of an output clock thereof is a multiple of the frequency of an input clock in general. FLL incorporates a frequency comparator and a variable-frequency circuit, by which control is performed so that the frequency of a feedback clock resulting from frequency division of an output clock, by which the frequency is made equal to the output clock frequency times the reciprocal of a multiplication number, is essentially locked to the frequency of an input clock. For an input clock to FLL, a relatively low frequency (about 32 kHz) generated by e.g. a quartz oscillator for RTC (Real Time Clock) is used. In general, FLL performs control so that only the frequency of an output clock multiplied with a multiplication number of a one-step higher level in comparison to PLL is made a fixed value. Therefore, the pulse edge of a feedback clock resulting from frequency division of the output clock, by which the frequency is equal to the output clock frequency times the reciprocal of a multiplication number, is not necessarily locked to the phase of edge of the input reference clock. However, FLL can be constructed with only a basic logic cell circuit readily, and therefore its output clock of a high frequency, which can be varied appropriately, can be used as a reference clock of original oscillation.
Of the circuits described above, a PLL (Phase Locked Loop) circuit is often used to reduce the skew of a clock signal arising at the time of distributing the clock signal an internal circuit of LSI. In general, a PLL circuit includes a phase-frequency comparator, a combination of charge pump and loop filter modules, a voltage or current control oscillator, and an analog circuit used as a buffer. In a PLL circuit, a clock input signal and a clock output signal of the buffer are supplied to the phase-frequency comparator, and an output of the phase-frequency comparator is supplied to the voltage or current control oscillator through the combination of charge pump and loop filter modules, whereby the phase difference between the clock input signal and clock output signal is made zero outwardly and thus the skew of the clock signal is reduced.
In the sleep mode of the internal circuit of LSI, clock supply by a PLL circuit is stopped, whereas the clock supply by the PLL circuit is resumed at the time of resuming the operation of the internal circuit in the active mode. However, to make the PLL circuit resume the clock supply, a lock time (settling time) until the frequency reaches a target frequency to become stable is needed, and high-speed restore from the sleep mode to active mode is needed.
PLL and DLL (Delay Locked Loop) for resolving the problem of skew of clocks are disclosed by Guang-Kaai Dehng et al., “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, PP. 1128-1136, AUGUST 2000. It further contains the description about an analog DLL and a digital DLL, and discloses the following points. Analog DLLs are not suitable for future low-power applications because sufficient delay time cannot be achieved with a low source voltage. In addition, analog DLLs tend to be affected by the variation of a manufacturing process and are vulnerable to noise coming from a power source. Digital DLLs are resistant to influences of noise coming from a power source, a manufacturing process, a voltage, a temperature, and a load (PVTL). Also, digital DLLs are lower in standby current consumption and shorter in lock time in comparison to analog DLLs.
Further, Guang-Kaai Dehng et al. disclose a binary search algorithm (a binary search method) to reduce a search time for lock by a digital DLL, and a digital DLL for successive approximation register (SAR) control which has a faster lock time in comparison to digital DLLs for register control and counter control. Also, it is described that in case of using 6-bit delay line, the digital DLL for SAR control ideally has a lock time of 6-clock cycle, and maintains tight synchronization even with a long clock distribution length, and makes possible to shorten the lock time.
A digital control oscillator used for a digital PLL disclosed by Robert Bogdan Staszewski et al, “Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicron CMOS Process”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003 PP. 815-828. The oscillator includes lots of quantized capacitances digitally controlled in an LC-tank of the oscillator.
Still further, a frequency multiply circuit is disclosed by Rafael Fried et al, “A High Resolution Frequency Multiplier for Clock Signal Generation”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, PP. 1059-1062, July 1996, which has a digital control oscillator including a highly accurate 14-bit current output type digital-to-analog conversion circuit (DAC) and which uses a binary search algorithm to lock an output clock to a frequency resulting from multiplication by a large multiplication number from the RTC frequency of an input clock. The RTC frequency is 32768 kHz, and the frequency resulting from the multiplication by the large multiplication number on the frequency of the output clock ranges 40 to 60 MHz.
Now, as well known, in a successive comparison type A/D converter, a successive approximation register (SAR) is connected between an output of a comparator and an input of a local D/A converter, and an analog input signal and an analog output signal of the local D/A converter are supplied to one input terminal of the comparator and the other input terminal thereof. Data held by the successive approximation register (SAR) is successively updated according to the binary search method so that the level of the analog output signal of the local D/A converter is coincident with the level of the analog input signal. Thus, digital conversion output signal of the analog input signal can be gained from the successive approximation register.